Besides being impacted by quantum confinement effects, the channel electrostatics of ultra-thin-body silicon-on-insulator (SOI) MOS devices, with channel thicknesses less than 10 nm, are also likely to be impacted by interface trap states. In this work, we comprehensively investigated the effect of band edge energy (surface passivation energy) on the band structure of the silicon channel. We propose to utilize this band edge energy ( ΔEedge) to study the effect of interface traps on device electrostatics, which is generally used to passivate the channel/oxide interface. First, by using sp3d5s∗ semi-empirical tight-binding methodology with a fully passivated interface ( ΔEedge>5 eV) and by including suitable bandgap correction for different device temperatures, the band structure is obtained, which is solved self-consistently with Poisson’s equation to accurately determine the channel electrostatics, without the effect of trap states. Interface trap states are now seen in the band structure through suitably varying the edge energy ( −5eV<ΔEedge<5 eV) based on which the interface trap density ( Dit) and the interface trap charge density ( Qit) are determined. Through incorporating Qit in the boundary condition for solving Poisson’s equation self-consistently with the band structure, channel electrostatics is recomputed to analyze the effect of traps for a wide range of device conditions. Finally, the degradation in the integrated charge density due to interface traps is accurately modeled for different SOI channel thickness and device temperatures.
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