Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction

摘要

This work presents a novel structure of Nanotube Tunnel FET in which a high-/c dielectric pocket is placed at the drain side to improve DC performance of the device. Using 3D TCAD simulation, it is shown that when a dielectric pocket (DP) is inserted at partially scaled drain region of Nanotube Tunnel FET at channel-drain interface then tunneling width at the output tunneling interface attains a maximum value for an optimum length and diameter of DP (i.e., 30 and 3 nm, respectively) which eventually reduces the ambipolar current up to a large extent. Furthermore, the subthreshold leakage current is also found to be reduced with the inclusion of DP in Nanotube Tunnel FET, thereby improving the current switching ratio (I_(on)/I_(off)- Additionally, the impact of varying k-value of DP on various DC parameters of the proposed device is demonstrated in this work and it is found that DP with high k-value reduces the ambipolar and subthreshold leakage current more as compared to the low-k DP. Moreover, the inclusion of DP dose not degrade the ON-state performance of Nanotube Tunnel FET as it has no significant impact on the rate of charge carriers tunneling through channel-drain interface during On-state.