The QCA technology is a strong contender for replacing CMOS technology in the design of nanoscale digital circuits. The goal of this paper's design is to increase the performance of the multiplexer (MUX) circuit. The design strategy is using a cost-effective architecture and path-planning design, which can reduce design costs. This paper presents an efficient circuit for 2-to-1 QCA MUX. Then, two circuits including 4-to-1 and 8-to-1 QCA MUX circuits are developed using this 2-to-1 QCA MUX circuit. The functionality of these circuits is investigated using QCADesigner tool version 2.0.3. The designed 2-to-1 QCA MUX circuit has 0.5 clock cycles delay, 0.01 mu m2 area and 15 cells. Moreover, the suggested 4-to-1 (8-to-1) QCA MUX circuit has 53 (163) cells, 0.06 (0.18) mu m2 area and 1 (3.75) clock cycles delay. The energy dissipation (Area-delay cost) of the proposed 2-to-1, 4-to-1, and 8-to-1 MUX at 1oK is 8.91 mev (0.04), 17.9 mev (0.96), and 39.3 mev (8.82), respectively. The comparison results demonstrate that the designed circuits provide benefits compared to other MUX circuits.(c) 2023 Elsevier B.V. All rights reserved.
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