机译:Highly Concurrent Latency-tolerant Register Files for CPUs
Inst Res Fundamental Sci IPM, Sch Comp Sci, Farmanieh Campus 70,Next Kouhe Nour Bldg, Tehran, Iran;
Univ Michigan, Dept Elect Engn & Comp Sci, 2260 Hayward St 4620 CSE, Ann Arbor, MI 48109 USA;
Sharif Univ Technol, Dept Comp Engn, Azadi Av, Tehran, IranEPFL ENT I ECOCLOUD, INJ 233,Batiment IND,Stn 14, CH-1015 Lausanne, SwitzerlandCarnegie Mellon Univ, Elect & Comp Engn Dept, 5000 Forbes Ave, Pittsburgh, PA 15213 USASwiss Fed Inst Technol, Informat Technol & Elect Engn Dept, Gloriastr 35, CH-8092 Zurich, Switzerland;
GPUs; register files; bank conflicts; register renumbering; latency tolerance; parallelism; high performance;