机译:High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit
Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar;
DPWM; digital pulse width modulator; decoder; synchronous reversible counter; synchronous phase shifted circuit; reversible synchronous sequential counter; D-flip flop; delay line output duty cycle; linearity; time resolution;