Design and verification of an ARM Watchdog Timer using UVM

摘要

The watchdog timer is an advanced microcontroller bus architecture (AMBA) compliant system-on-chip peripheral. It is an AMBA slave module and connects to the advanced peripheral bus (APB). It consists of a 32-bit down counter with a programmable timeout interval that generates an interrupt and applies a reset to the processor on time out. Verification intellectual property (IP) is a smart way to verify the functional correctness of any complex design. This is achieved by constrained random verification (CRV), which generates legal test scenarios randomly that weed out the bugs and corner cases, thereby validating the characteristic features of the watchdog timer. CRV also builds automated checkers and provides higher coverage goals. In this work, an ARM Watchdog Timer is designed in Verilog and system-on-chip level verification of the same is performed using the universal verification methodology (UVM) by combining both CRV and coverage driven verification (CDV) to ensure its functional correctness.