A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications

摘要

Power consumption and image resolution are the major concerned while designing modern readout integrated circuits (ROICs) of Cadmium-Telluride (CdTe)/Cadmium-Zinc-Telluride (CdZnTe) sensors for nuclear magnetic resonance imaging (MRI) and positron emission tomography (PET) applications. The key ROIC element, namely, preamplifier, must be monolithically integrated to the sensor chip and should guarantee low noise, low power, and high linearity along with assuring higher conversion gain and less chip area. A power immune, linear charge sensitive preamplifier (CSP) with a custom leakage current compensation feedback for (CdTe)/CdZnTe sensors is designed. A maximum power consumption of 120 mu W, stable against process voltage and temperature (PVT) variations, is achieved. The compensation module cancels out current noise generated at the output of the circuit, lowering the power spectral density of about 84.26% than that of similar architectures, thus improving the signal-to-noise ratio (SNR) at the CSP output by a factor of 6.31. In turns, it injects about 100 pA of input direct-current (DC) current and compensates the sensor leakage current therefore. Two input dynamics of (0.25-10) and (10.01-20)fC are achieved, providing two conversion factors of 23.06 and 19.00 mV/fC with 2.4% and 0.58% nonlinearity errors, respectively, using 1 pF sensor capacitance. Noise performance of the circuit is improved with 47.5 e-rms and 62.46e-rms of equivalent noise charge (ENC) depending upon the input dynamic. The design is validated by Monte Carlo simulations and PVT analysis implemented in 65 nm complementary metal-oxide semiconductor (CMOS) process, assuring a chip area of only 0.000246 mm(2).