机译:Multistage pipelined architectures of Piccolo cipher for high-speed IoT applications
Department of Electronics and Communication Engineering, National Institute of Technology;
Department of Microelectronics and VLSI, CSVTU Bhilai;
School of CSE, VIT-AP University;
IoT; Internet of Things; FPGA; field programmable gate array; throughput; Feistel structure; cryptography; RFID; Piccolo; ASIC; gate equivalent;