25.6 Tbps Capacity and Sub-μsec Latency Switching for DataCenters Using amp;1000-Port Optical Packet Switch Architectures

摘要

We discuss the challenges and limitations of current electrical DataCenter switches towards scaling beyond the 25.6?Tb/s capacity-era while meeting a low-latency and high-radix envelope. With the high-power SerDes and required DSP interfaces forming critical scaling factors, we discuss the perspectives and challenges of migrating to Optical Packet Switch (OPS) technologies for avoiding the electronically-induced bottlenecks, while exploiting reliable and practical techniques for overcoming well-known OPS problems, like buffering and high-port connectivity. We demonstrate the feasibility of OPS schemes by reporting experimental results of our Hipoλaos architecture towards extending its line-rate to 25?Gb/s per port and enabling 25.6?Tb/s switch capacities through a 1024-radix layout, while still preserving sub-μs latency metrics. Experimental results are presented for both unicast and multicast packets, employing the 1024-radix Hipoλaos architecture in a fully-fledged FPGA-controlled switching Plane, along with a 32?×?32 Arrayed Waveguide Grating Router (AWGR) device. The unicast performance is validated through BER measurements, while optical multicasting to 5 nodes is also experimentally evaluated at 25?Gb/s, along with an evaluation of the broadband multicast capabilities of the switch. Moreover, a mixed-traffic scenario involving both unicast and multicast traffic is demonstrated. Finally, a discussion about the perspectives and challenges of bringing OPS in DC networks is presented.