The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.
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