A 70 Mhz Multiplierless Fir Hilbert Transformer In 0.35μm Standard Cmos Library

摘要

This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-DF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap HR Hilbert transform digital filter was implemented and fabricated in 0.35 μm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm~2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.