A novel channel resistance ratio method for effective channel length and series resistance extraction in MOSFETs

摘要

A resistance ratio method for electrical effective channel length and series resistance extraction is developed and verified on an advanced 0.35 μm LDD CMOS technology. This method avoids the gate bias range optimization required in the widely used "shift-and-ratio" (S&R) method, which is usually technology specific, while retaining the single transistor algorithm nature of S&R.