The adoption of high-speed serial data interfaces and the move to smaller semiconductor manufacturing geometries is necessary for cost, integration, and performance factors, but this smaller geometry is also more prone to ESD damage at lower voltage and current levels. Additionally, low-capacitance ESD devices required on high-speed data lines tend to have higher dynamic resistance as their capacitance decreases, making them less capable of protecting sensitive ICs in the system. With traditional ESD protection, an inverse relationship exists between robust ESD protection and good signal integrity. Some ASICs have no acceptable traditional ESD device that can provide required ESD protection levels combined with acceptable signal integrity.
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