With ever-shrinking feature geometries, multilevel IC interconnects will greatly influence overall circuit behavior. In particular, efficient numerical evaluation of 3D IC-interconnect capacitance is essential to achieving targeted design goals.Previously. we have reported a new random-walk (RW) algorithm for extracting capacitance of complex multilevel IC interconnects [see, Y.L. Le Coz and R.B. Iverson, So/id-St. Electron. 35, 1005 (1991)). Here, for the first time, we present a numericalstudy concerning the influence of interconnect complexity on RW-extractor performance. Of primary interest, are the empirical relationships among geometric complexity, run time, and memory usage. We also include. for reference, comparisons withconventional finite-element (FE) and boundary-element (BI) capacitance extractors. Despite the general computational limitations of these conventional extractors, we have attempted to normalize numerical errors to a single common value. The problemgeometry selected for our study consists of a long "bus" wire situated beneath a series of shorter cross wires Problem complexity is controlled by increasing the bus-wire length and adding cross wires. We have found that at 1 % normalized error inbus-wire self-capacitance. the RW extractor has the shortest execution time, which is uniquely independent of problem complexity. In addition, because the RW extractor requires no numerical meshing. an RW:BI;FE memory-usage ratio of 1:10{sup}3:10{sup}7was observed. We conclude that the RW method may possibly excel in the high-complexity regime characteristic of multilevel IC interconnects.
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