机译:良率驱动的时钟偏斜调度,用于关键路径延迟的任意分布
State Key Lab. of ASIC & System, Microelectronics Dept., Fudan University, Shanghai, China;
Iowa State University, USA.;
State Key Lab. Of ASIC & System, Microelectronics Dept., Fudan University, Shanghai, China;
yield-driven; clock skew scheduling; generalized howard algorithm; generalized minimum balance algorithm;