In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QC1F) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35 power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32 computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.
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