Design of Low Power Reduced Delay Fixed-Width Modified Booth Multiplier

摘要

This paper presents a design of low power reduced delay fixed-width booth multiplier for multimedia and communications systems. This multiplier architecture is based on radix-4 booth multiplier. We introduce decomposition logic in the proposed fixed-width booth multiplier architecture to improve the delay and power consumption. The design is developed by using Verilog-HDL and synthesized using a Cadence tool for Area, Power and Delay estimation of proposed architecture as well as existing architecture. This result shows that the proposed architecture consumes less power consumption and delay as compared to the existing architectures.