A hardware in the loop emulator for a satellite control system

摘要

Design and testing of algorithms for satellite attitude control is not an easy task. Once the system is deployed (the satellite is launched), there is no room for error or system modifications. That, of course, requires extensive testing and simulation before deployment. However, simulation can not capture all aspects of system operation. For example, capturing jitter in the system due to hardware issues such as cache miss, interrupts, dynamic scheduling, or instruction prediction is almost impossible. In such a case, hardware in the loop (HiL) simulation platform is used to capture real-time system behaviour. In this paper, we propose and implement a HiL simulator for a small satellite on FPGA. The model implements the satellite dynamics as well as jitter and noise added to the signal. We use our emulator to study the effect of fixed point implementation on the controller performance. Our results indicate that we can achieve a 50% power saving using fixed point implementation (as compared to floating point implementation) with almost no performance degradation. We also use the HiL platform to test the effect of noise and jitter on the system performance.