Development of burst-mode bit synchronization circuit for Gbit/s transmission systems

摘要

We developed a burst bit synchronization circuit that can afford much pulse width distortion in burst optical receivers, in order to reduce the Ethernet-passive optical network (PON) system cost complied with IEEE802.3ah specification [1]. This paper describes the detail consideration concerned with the sampling number, the conditions of lock-in and the method of keeping the adequate phase for data recovery. We developed an experimental circuit and examined on the performance. As a result, these were confirmed the tolerance of ±64% pulse width distortion and 40ns lock-in time. They are enough value to design economical optical receivers.