High Performance AXI Protocol Based Improved DDR3 Memory Controller With Improved Memory Bandwidth

摘要

The DDR3 Memory has backward compatibility with existing DDR2 Memory and power saving advantage. To increase the performance of DDR3 memory controller, we fire read/write transaction with High speed so require High-speed AXI (Advance extensible Interface) Bus. This paper deals with the high performance AXI protocol based improved DDR3 memory controller with improved memory bandwidth. In this paper, controller clock frequency is 400 MHz and CAS Latency is 10.