Modeling of power consumption for super-cell based on statically substrate-biased domino CMOS circuit

摘要

We proposed a circuit scheme making the most of pull-up/pull-down transistors with high threshold voltages by static substrate-biases. Here, the source terminals of these transistors were only connected to the base of power supply and ground. We reduced the area of domino CMOS circuits only with NMOS having a low threshold voltage and without its PMOS [1,2,3]. Furthermore, in order to achieve a quick timing closure, we proposed the layout architecture of super-cell of the domino CMOS circuits with continuously variable transistor width which can correspond to the output load of interconnection RC [4,5,6]. Also, we improved the above layout architecture for AO23 (2-input AND/3-paralallel OR) as a typical cell and re-established the delay model [7]. In this paper, we investigate a power consumption model for the sluper-cell to three independent measures of transistor width, intereconnection RC, and fanout capacitance, using a circuit simulator based on the BSIM3v3 model of 0.35 μm CMOS process.