Super-cell design based on statically substrate-biased domino CMOS circuit I: cell layout architecture with continuously variable transistor width

摘要

Using another static substrate-bias [V{sub}(DD)'(> V{sub}(DD)), V{sub}(SS)'(< V{sub}(SS))] in addition to common power supply [V{sub}(DD), V{sub}(SS)], we proposed a circuit scheme making the most of pull-up/pull-down transistors with high threshold voltages (V{sub}(TN)', V{sub}(TP)'), which are biased by [V{sub}(DD)', V{sub}(SS)']. Here, the source terminals of these transistors were only connected to the base of [V{sub}(DD), V{sub}(SS)]. We reduced the area and delay time of domino CMOS circuit by not using the PMOS transistor with low V{sub}(TP) biased by V{sub}(DD) on n-well [1,2]. In this paper, being based on this circuit, we propose the super-cell layout architecture with continuously variable transistor width. We study the circuit performance of area, delay time and power consumption for the inverter and AOI24, compared to their static CMOS circuits, by using a circuit simulator based on the BSIM3v3 model of 0.35 μm CMOS process.