Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${rm GF}(2^{163})$

摘要

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements, we reorganize and reorder the critical path of the Lopez–Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with $G=55$ our proposed design is able to compute scalar multiplication over ${rm GF}(2^{163})$ in 9.6 $mu{rm s}$ with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where $G$ is the digit size of the underlying digit-serial finite-field multiplier. Another implementation variant for less resource consumption is also proposed; with $G=33$, the design performs the same operation in 11.6 $mu{rm s}$ at 263 MHz on the same platform. The results of synthesis show that, in the first implementation, 17 929 slices or 20% of the chip area is occupied, which makes it suitable for speed-critical cryptographic applications, while in the second implementation 14203 slices or 16% of the chip area is utilized, which makes it suitable for applications that may require speed–area tradeoff.