FPGA Implementation of Error Reduction in Energy-Efficient Truncation and Rounding-Based Scalable Approximate Multiplier

摘要

An approximation approach of scalable approximate multiplier using truncated and rounding-based technique is presented to reduce the number of partial products based on leading 1 bit position. The multiplication design is performed using arithmetic unit, truncation unit, absolute unit, shift unit for shift and add accumulation. The operation of TOSAM(3,7) contains more absolute error. This design methodology will modify all the arithmetic operations of shift and add unit and reduce the absolute error. This design is proved in higher improvements of area and energy consumptions. Finally, the work is designed in Verilog HDL and simulated and synthesized in Xilinx ISE.