Three obstacles in particular bedevil IC designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then, as the number of logic gates per chip passes the million mark, verification of a design's correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money.
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