An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS

摘要

This article presents a clock-domain-based integrated pulsewidth modulation (PWM) (iPWM) line-coding scheme to enable equalization while operating at low supply voltages. While conventional equalizers such as feedforward equalizer (FFE), decision feedback equalizer (DFE), and continuous-time linear equalizer (CTLE) are present on the high-bandwidth data path, the proposed iPWM-based line-coding-based approach moved the equalization logic away from the data path and into the subrate clock path. As a result, the proposed clock-domain iPWM line coding can operate at low supply voltages. An energy-efficient implementation of the proposed scheme was demonstrated. Fabricated in a 65-nm CMOS process, the proposed transceiver operates over a data-rate range of 3-16 Gb/s from 0.5 to 0.9 V. Equalization in this transceiver was done using iPWM and a passive CTLE. Operating at 10 Gb/s at 0.65 V, the proposed transceiver is capable of equalizing up to 27 dB of channel loss at energy efficiency of 1.8 pJ/bit.