A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking

摘要

This paper reports a 32-unit phase-locked dense heterodyne receiver array at f(RF) = 240 GHz. To synthesize a large receiving aperture without large sidelobe response, this chip has the thllowing two features. The first feature is the small size of the heterodyne receiver unit, which is only lambda(fRF)/4 x lambda(fRF)/2. It allows for the integration of two interleaved 4 x 4 arrays within a 1.2 mm(2) die area for concurrent steering of two independent beams. Such unit compactness is enabled by the multi-functionality of the receiver structure, which simultaneously accomplishes local oscillator (LO) generation, inter-unit LO synchronization, input wave coupling, and frequency down conversion. The second feature is the high scalability of the array, which is based on a strongly coupled 2-D LO network. Large array size is realizable simply by tiling more receiver units. With the upscaling of the array, our de-centralized design, contrary to its prior centralized counterparts, offers invariant conversion loss and lower LO phase noise. Meanwhile, the entire LO network is also locked to a 75-MHz reference, facilitating phase-coherent pairing with external sub-terahertz transmitters. A chip prototype using a bulk 65-nm CMOS technology is implemented, with a dc power of 980 mW. Phase locking of the 240-GHz LO is achieved among all 32 units, with a measured phase noise of 84 dBc/Hz (1-MHz offset). The measured sensitivity (BW = I kHz) of a single unit is 58 fW. Compared to previous square-law detector arrays of comparable scale and density, this chip provides phase-sensitive detection with--4300x sensitivity improvement.