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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision
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A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision

机译:具有高灵敏度的1 / 2.5英寸VGA 400 fps CMOS图像传感器,适用于机器视觉

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Machine vision requires CMOS image sensors (CISs) with high frame rate, short exposure time, and fine spatial resolution. Recently, capacitive transimpedance amplifier (CTIA) is used in the high-speed pixel circuit to achieve high sensitivity by expediting the charge transfer from the photodiode to a tiny integration capacitor (${rm C} _{rm INT}$). Existing CTIA pixel designs have large pixel sizes due to the multiple sampling capacitors and switches for global shutter and CDS, which unfavorably limits the spatial resolution. In this paper, we present a 400 fps CIS design with 640 × 480 pixel array for machine vision. With simplified pixel circuits, the new sensor has a CTIA pixel size of 8.7 × 8.22 µm 2 , which is the smallest in the category. The pixel implements a new multi-layer MOM capacitor with good uniformity as the tiny ${rm C} _{rm INT}$ , which achieves high sensitivity (36.5 V/lux·s) without calibration. Pixel-wise CDS is implemented in this global-shutter CIS to minimize the pixel noise. The pixel signals are quantized by 640 column processing slices with 12 bit resolution at 411 kS/s. The size of the column SAR ADC is minimized with a simple calibration technique. The CIS is fabricated in a 0.18 µm mixed-signal CMOS process. The temporal noise is 15.6 e$ ^{-} _{rm rms}$. With the new MOM capacitor, FPN of the CIS is 0.55% without calibration. The new pixel design achieves the highest sensitivity per unit area.
机译:机器视觉需要具有高帧频,短曝光时间和精细空间分辨率的CMOS图像传感器(CIS)。最近,在高速像素电路中使用了电容互阻放大器(CTIA),以通过加快从光电二极管到微型积分电容器的电荷转移来实现高灵敏度(<公式公式类型=“ inline”> $ {rm C} _ {rm INT} $ )。由于用于全局快门和CDS的多个采样电容器和开关,现有的CTIA像素设计具有较大的像素尺寸,这不利地限制了空间分辨率。在本文中,我们提出了一个640×480像素阵列的400 fps CIS设计,用于机器视觉。通过简化的像素电路,新传感器的CTIA像素尺寸为8.7×8.22 µm 2,在同类产品中是最小的。该像素实现了一个具有良好均匀性的新型多层MOM电容器,该电容器具有微小的 $ {rm C} _ {rm INT} $ ,无需校准即可实现高灵敏度(36.5 V / lux·s)。在此全局快门CIS中实现了逐像素CDS,以最小化像素噪声。像素信号通过411 kS / s的12位分辨率的640列处理切片进行量化。列SAR ADC的尺寸可通过简单的校准技术最小化。 CIS采用0.18 µm混合信号CMOS工艺制造。时间噪声为15.6 e <公式公式类型=“ inline”> $ ^ {-} _ {rm rms} $ 。使用新的MOM电容器,无需校准即可使CIS的FPN为0.55%。新的像素设计可实现最高的单位面积灵敏度。

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