0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

摘要

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz.