A 0.5 V Operation $V _{rm TH}$ Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems

摘要

A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage ($V _{rm DD}$) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on $V _{rm DD}$. When the 0.5 V $V _{rm DD}$ is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the $V _{rm TH}$ variation. DRAM has a potential to operate at such low $V _{rm DD}$. As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 $muhbox{m}$ standard CMOS process and the high-speed boosting is experimentally demonstrated.