A low-power gate driver integrated by IZO- TFTs employing single negative power source

摘要

This paper proposes a new gate driver employing only a single negative power source, which is integrated by In-Zn-O TFTs with an etch stop layer (ESL) structure. A negative voltage generating module (NVGM) is developed to generate a lower voltage level than that of the negative power source, in order to completely shut down the pull-down transistors of the output module. 30 stages of the proposed gate driver are fabricated on glass substrate. It is shown that the gate driver successfully achieves full swing output signals at different clock frequencies (6.67 kHz, 66.7 kHz) and negative power sources (-4 V, -5 V, -6 V) with resistive load R-L = 3 k Omega and capacitive load C-L = 30 pF. The measured power consumption per stage of the proposed gate driver is 101 mu W at the clock frequency of 66.7 kHz.