Beyond the 1G limit, new device structures will be required. Based on the inherent advantages of the SOI substrate where substrate leakage can be eliminated by removing the leaky path through the silicon substrate, several transistor structures have been proposed including the single-gate fully depleted transistor (DST), double-gate transistor FinFET, planar double-gate transistor, and tri-gate fully depleted transistor. The FinFET is built by thinning the silicon layer on the buried oxide layer of the SOI wafer down to a few tens of nanometers, then etching it to form a narrow vertical fin that sticks up from the wafer surface. The channel of the device is formed in the fin, which rests on the insulator. Source and drain electrodes are built at each end of the fin and the gate drapes over both of its sides.
展开▼
