Packaging for Nanometer-Scale Silicon

摘要

The advent of the 130 nm node introduced the use of copper metallization and low-k dielectrics, promising faster performance, smaller chip sizes and lower power consumption. Over the past few years, integrating low-k dielectrics has become a greater challenge than originally anticipated. Along with the process development issues of copper metal stacks and low-k dielectrics are the complexities of the package material system and its interaction to the overall reliability of the finished product. Although many companies have abandoned the use of true low-k dielectrics at the 130 nm node, there have been some success stories. Today, system-on-chip (SoC) designs are in production using low-k dielectrics and copper interconnects at the 130 nm node. Critical to the success of flip-chip and wire-bond interconnect with cop-per/low-k silicon is mechanical stress modeling leading to the characterization ot package materials and assembly processes compliant to the mechanical integrity requirements of copper/low-k silicon interconnect technology. The 130 nm node signals a new era of co-design between packaging engineers and silicon process developers, who have successfully overcome the challenges of nanometer-scale product design.