A holistic approach to analyze Ultra-lot variation on overlay data

摘要

In semiconductor manufacturing, intra-lot (wafer-lo-wafer) variation is getting more and more attention since it is dominating the on-product overlay performance. There has been knowledge about wafcr-to-wafer contributions from different domains: alignment strategy can have impact on the fingerprint variation; scanner performance is a contributor to the intra-lot performance; metrology quality, e.g. measurement noise, can contribute to wafer-to-wafer variation as well. Some strategies may improve intra-lot performance, typically based on detailed analysis of performance and context data. However it may be difficult to gel a full picture of potentially available solutions to improve the performance of a semiconductor manufacturing process: 1) the analysis result may depend on the knowledge level and the analysis habit of the engineer performing the analysis, 2) lack of overview of the contributors to variations, and 3) the solutions from one knowledge domain might be sub-optimal.