首页> 外文期刊>Radar, Sonar & Navigation, IET >Memory-based two-dimensional-parallel differential matched filter correlator for global navigation satellite system code acquisition
【24h】

Memory-based two-dimensional-parallel differential matched filter correlator for global navigation satellite system code acquisition

机译:基于存储器的二维并行差分匹配滤波器相关器用于全球导航卫星系统代码获取

获取原文
获取原文并翻译 | 示例
           

摘要

This study presents a code acquisition architecture for a global navigation satellite system (GNSS). The proposed scheme aim to reduce buffer resource required without reducing the number of code, frequency and satellite bins. Therefore the GNSS signal has no information loss. The code acquisition process in a GNSS attempts to find the code phase of a satellite signal, and it includes three procedures: coherent integration (CI), correlation and in CI. The proposed code acquisition architecture provides a lower operation count for correlation with reduced memory consumption. Firstly, the memory in CI and the shift register in the correlator are integrated by changing the operation sequence of CI and correlation. Thus, half of the memory in CI can be removed, and the shift register becomes the sharing buffer for both correlation and CI. Secondly, the addition count in the correlation is reduced by combining a parallel differential matched filter (PDMF) with a two-dimensional (2D) architecture to form a memory-based 2D-PDMF correlator. Finally, changing the sample sequence before integration reduces the memory of in CI. Compared with conventional code acquisition, the proposed design can reduce register consumption by 80% and addition count by 60% operation count for correlation and 50% memory consumption of incoherent integration.
机译:这项研究提出了一种用于全球导航卫星系统(GNSS)的代码获取架构。所提出的方案旨在减少所需的缓冲器资源而不减少代码,频率和卫星箱的数量。因此,GNSS信号没有信息丢失。 GNSS中的代码获取过程试图找到卫星信号的代码相位,它包括三个过程:相干积分(CI),相关和CI。所提出的代码获取体系结构提供了较少的操作次数以实现相关性,同时减少了内存消耗。首先,通过改变CI和相关的操作顺序来集成CI中的存储器和相关器中的移位寄存器。因此,可以删除CI中一半的存储器,并且移位寄存器成为相关性和CI的共享缓冲区。其次,通过将并行差分匹配滤波器(PDMF)与二维(2D)架构组合以形成基于内存的2D-PDMF相关器,可以减少相关性中的相加计数。最后,在积分前更改样品序列会减少CI中的内存。与常规代码获取相比,该设计可以将寄存器消耗减少80%,将附加计数减少60%,以实现相关性,并减少不相干集成的50%内存消耗。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号