On topology diagrams, we can easily visualize or specify the delays between any driver/receiver pair on multi-point nets. Some standards specify PCB design rules this way, for example, DDR-SDRAM DIMM memories (various Jedec JESD21-C documents) or Chipset Design Guides. Some design programs specify the constraints on these diagrams, like the Cadence Allegro Signal Explorer. The topology may be defined graphically, or as a spreadsheet for the point-to-point min./max. or relative length rules,rnAdd-in cards: If a bus is routed through multiple boards, then the timing and length rules have to be correct for the whole system together (FIGURE 20). If different individuals or companies design the boards, they have to agree in the way of dividing the constraints between the boards, as a form-factor standard. In case of a clock tree, if the add-in card clock trace length is closely the same for all cards, then the skew can be controlled only by the motherboard design.
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机译：在拓扑图上，我们可以轻松地可视化或指定多点网络上任何驱动器/接收器对之间的延迟。一些标准以这种方式指定PCB设计规则，例如DDR-SDRAM DIMM存储器（各种Jedec JESD21-C文档）或芯片组设计指南。一些设计程序会在这些图上指定约束，例如Cadence Allegro Signal Explorer。拓扑可以图形方式定义，也可以定义为点对点最小/最大的电子表格。或相对长度规则，附加卡：如果总线通过多块板布线，则时序和长度规则必须对整个系统一起正确（图20）。如果不同的个人或公司设计董事会，则他们必须同意在董事会之间划分约束的方式，作为一种形式因素标准。如果是时钟树，如果所有卡的附加卡时钟走线长度都几乎相同，则只能通过母板设计来控制偏斜。
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