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摘要

"Scalable 3D-FPGA Using Wafer-to-Wafer TSV Interconnect of 15 Tbps/W, 3.3 Tbps/mm2" Authors: F. Furuta, T. Matsumura, K. Osada, M. Aoki, K. Hozawa, K. Takeda and N. Miyamoto Abstract: A scalable 3D-FPGA using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An embedded TSV design for the shorter on-chip wirings was also devised.