Frequency reduction schemes for back-to-back connected, diode-clamped multilevel converters

摘要

Two new switching schemes for back-to-back connected diode-clamped multilevel converters that reduce the devices switching frequency while maintaining capacitor balancing are presented. Comparisons are made between a previously reported `optimal` balancing strategy and the two proposed switching techniques using data gathered from a prototype five-level, back-to-back connected, diode-clamped multilevel converter. The proposed schemes are shown to allow as much as 35` reduction in switching frequency when compared to the optimal balancing case while also balancing the voltages across the series connected DC-link capacitors. The back-to-back connected, multilevel converter excites a permanent magnet synchronous motor to obtain the experimental data and verify the proposed switching schemes.