Common mode voltage suppression in three-phase voltage source inverters with dynamic load

摘要

This study proposes a novel pulse width modulation (PWM) algorithm to mitigate the common mode voltage (CMV) in a multi-level voltage source inverter feeding an electric machine. Dead-time effect frequently prevents the CMV not to reach zero in several switching periods. Then the electromagnetic interference noise is generated and causes bearing failure and overvoltage stress on winding insulations. The proposed strategy compensates the dead-time effect that alleviates the high-amplitude rectangular pulses with extreme range of variations during high-frequency switching transitions. The existing PWM methods reduce the CMV to $ pm V_{{m dc}}/6comma ; $+/- Vdc/6, however by utilising the presented approach, CMV can be reduced to zero. However, the total harmonic distortion will be increased 0.3% at fundamental current harmonic rather than conventional state PWM method, which could be neglected. Simulation results and efficiency analysis imply on worthy performance of the proposed strategy to eliminate the CMV.