System architecture of Detector Control and safety for the ATLAS Inner Detector Upgrade

摘要

In the current ATLAS Upgrade plan a new Inner Detector (ID) based upon silicon sensor technology is being considered. The operational monitoring and control of the ID will be very demanding. The Detector Control System (DCS) is a common tool that is essential for the operational safety of a system. Even at this early stage the DCS system architecture has to be defined such that it is well integrated and optimized for its later implementation and use. For example the DCS diagnostics for the front-end (FE) chips is a serious option being considered that needs an early requirement and specification definition. In addition one of the main constraints is the service reuse between the service patch panels of the ATLAS ID and the counting room that limits the number of electrical lines to be reused. Conceptual differences in terms of readout architecture and layout have been identified between the strip and the pixel detector that lead to two distinct architectures. Nevertheless, the limitation of available electrical lines going to the counting room as well as the low material budget requirements inside the ID volume are two major constraints that lead the ID to consider an on-detector radiation hard integrated circuitry for the slow control. At this stage of the project, the definitions of the logical actions and protocol for the ADCs of such a chip are still being specified. In addition the experience gained from the current ID will be essential for the guidance of tuning the future DCS architecture in the coming years.