Faster, smaller and lower cost

摘要

The demanding requirements of broadband infrastructure applications using xdsl, wireless and optical fibre technologies, along with the growth in high performance multimedia information systems, is putting pressure on developers to produce ever more complex system on chip (SoC) solutions. As oems seek to expand the performance and capabilities offered by portable, battery powered devices, there is also a growing need for advanced SoC solutions in these designs. This means developers must continually seek out faster asic technologies that offer higher gate densities whilst conserving board space and driving down power consumption. And all of this in an environment where time to market pressures and the need to deliver ahead of the competition are squeezing the time available for development and prototyping. The rapid evolution in the asic technology available to SoC developers can be seen by con- sidering Toshiba's asic roadmap. In 1997, for example, the company launched its TC240 family, based on the 0.25μm CMOS-1 process. Asics built around the TC240 featured a core power supply voltage of 2.5V and could achieve a gate density of around 36,000 gates/mm~2. Two years later, the 0.14μm CMOS-2 process allowed the launch of Toshiba's TC260 technology, with a gate density in excess of 125,000 gates/mm~2 and a core power supply voltage of 1.5V. The TC280 family, which followed in 2001, was based on the 0.13μm CMOS-3 process. With a gate length of 0.11μm, this increased possible gate density to more than 200,000 gates/mm~2. Most recently, Toshiba announced the TC300 asic technology.