Xilinx updates ISE Design Suite

摘要

As the first stage in the introduction of IP cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in SoC design, Xilinx has released ISE Design Suite 12.3.rnThe AXI4 protocol defines a point to point interface developed to address SoC performance challenges. It supports multiple clock domains, along with data up sizing and downsizing. The AXI4rnspecification also includes features such as address pipelining, out of order completion and multithreaded transactions.