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Phase Noise: Theory versus Practicality

机译:相位噪声:理论与实践

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摘要

Modern electronics rely on fast low noise time bases for a variety of applications. As a result, oscillator designers must always push the limit of low noise design. One of the major hurdles in this endeavor is phase noise. Phase noise is an undesirable entity that causes distortion and high bit error rates. It is therefore important to understand this phenomenon and reduce its effects on higher level systems. This article discusses different time bases and their properties, crystal oscillator properties, phase noise definition and calculations, ways to reduce phase noise in oscillator design, real oscillator phase noise plots, and outside noise/interference effects on phase noise. It will be shown that phase noise is unavoidable but manageable. Through careful oscillator design, phase noise can be reduced, and through informed consumer system design can accommodate the real world oscillator.
机译:现代电子产品在各种应用中都依赖快速的低噪声时基。结果,振荡器设计人员必须始终推动低噪声设计的极限。这项工作的主要障碍之一是相位噪声。相位噪声是导致失真和高误码率的不良因素。因此,重要的是要了解这种现象并减少其对更高级别系统的影响。本文讨论了不同的时基及其属性,晶体振荡器属性,相位噪声定义和计算,减少振荡器设计中相位噪声的方法,实际振荡器相位噪声图以及外部噪声/干扰对相位噪声的影响。将显示出相位噪声是不可避免的,但可以控制。通过精心设计的振荡器,可以减少相位噪声,并且通过明智的用户系统设计可以适应现实世界的振荡器。

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