A collision management structure for NoC deployment on multi-FPGA

摘要

With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than 10s, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of lOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs.