Eliminating etch-sequencing-induced dielectric defects in high volume manufacturing

摘要

Semiconductor manufacturers often employ unique practices in their fab operations resulting from their operational methodology, tool configurations, and known process sensitivities. To achieve effective tool utilization, they often configure their dry-etch tools for multiple processes, such as oxide, nitride, and spin-on-glass (SOG) dielectric etch. The interaction between these varied processes and their residual effects on chamber conditions can change process outputs and generate unique defects. Because the information available in traditional books and best-known methods generally does not help solve unconventional issues, fabs must resort to extensive investigations and experimentation to formulate solutions. This article presents a case study from National Semiconductor's fab in Arlington, TX, in which a residual contaminant from an upstream dry-etch process interacted with incoming material to produce localized spongy-looking SOG defects in a downstream interlev- el dielectric (ILD). The article discusses the origin of this unique defect, the process condi- tions that affect it, and various methodologies that can be used to monitor, control, and eliminate it. Finally, the article analyzes the defect's effect on various electrical test parameters and die yield.