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Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE

机译:Jacobi方法在异构平台上的模具计算:GPU与Cell BE

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摘要

We are witnessing the consolidation of the heterogeneous computing in parallel computing with architectures such as Cell Broadband Engine (Cell BE) or Graphics Processing Units (GPUs) which are present in a myriad of developments for high performance computing. These platforms provide a Software Development Kit (SDK) to maximize performance at the expense of dealing with complex and low-level architectural details which makes the software development a daunting task. This paper explores stencil computations in several heterogeneous programming models like Cell SDK, CellSs, ALF and CUDA to optimize the Jacobi method for solving Laplace's differential equation. We describe the programming techniques to extract the maximum performance on the Cell BE and the GPU, and compare their computing paradigms. Experimental results are shown on two Nvidia Teslas and one IBM BladeCenter QS20 blade which incorporates two 3.2 GHz Cell BEs v 5.1. The speed-up factor for our set of GPU optimizations reaches 3—A, x, and the execution times defeat those of the Cell BE by an order of magnitude, also showing great scalability when moving towards newer GPU generations and/or more demanding problem sizes.
机译:我们正在目睹并行计算中异构计算的整合与诸如蜂窝宽带引擎(Cell BE)或图形处理单元(GPU)之类的架构,这些架构存在于高性能计算的众多发展中。这些平台提供了软件开发工具包(SDK),以最大程度地提高性能,但以处理复杂的低级体系结构细节为代价,这使软件开发成为一项艰巨的任务。本文探索了几种异构编程模型(例如Cell SDK,CellSs,ALF和CUDA)中的模版计算,以优化Jacobi方法来求解Laplace微分方程。我们描述了在Cell BE和GPU上提取最大性能的编程技术,并比较了它们的计算范例。在两个Nvidia Tesla和一个IBM BladeCenter QS20刀片上展示了实验结果,该刀片结合了两个3.2 GHz Cell BE v 5.1。我们的一组GPU优化的加速因子达到了3A,x,执行时间比Cell BE的执行速度高出一个数量级,在朝着新一代GPU和/或更苛刻的问题迈进时,还显示出了出色的可扩展性大小。

著录项

  • 来源
    《Journal of supercomputing 》 |2012年第2期| p.787-803| 共17页
  • 作者单位

    Dept. of Computer Science, Catholic University of Murcia, Murcia, Spain;

    Dept. of Computer Engineering, University of Murcia, Murcia, Spain;

    Intel Barcelona Research Center, Intel Labs, Universitat Politecnica de Catalunya, Barcelona, Spain;

    Dept. of Computer Engineering, University of Murcia, Murcia, Spain;

    Dept. of Computer Engineering, University of Murcia, Murcia, Spain;

    Computer Architecture Department, University of Malaga, Malaga, Spain;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    hardware accelerators; GPGPU; CELL; stencil computations;

    机译:硬件加速器;GPGPU;细胞;模具计算;

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