Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

摘要

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a 'grassfire' transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomo-geneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.