Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems

摘要

In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output components that manage data transmission in a first-in, first-out (FIFO) fashion. In this paper, we formulate the vertices and edges into concepts called "active blocks" and "passive blocks", respectively in the graph representation. Computation in the dataflow graph is represented as "active blocks", while the concept of dataflow buffers is represented as "passive blocks". Like dataflow edges, passive blocks are used to store data during the intervals between its production and consumption by actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its application to improving memory management efficiency, and execution time performance.