Low latency complex event processing on parallel hardware

摘要

Most complex information systems are event driven: each part of the system reacts to the events happening in the other parts, potentially generating new events. Complex event processing (CEP) engines in charge of interpreting, filtering, and combining primitive events to identify higher level composite events according to a set of rules are the new breed of message-oriented middleware, which is being proposed today to better support event-driven interactions. A key requirement for CEP engines is low latency processing, even in presence of complex rules and large numbers of incoming events. In this paper, we investigate how parallel hardware may speed up CEP processing. In particular, we consider the most common operators offered by existing rule languages (i.e., sequences, parameters, and aggregates); we consider different algorithms to process rules built using such operators; and we discuss how they can be implemented on a multi-core CPU and on CUDA, a widespread architecture for general-purpose programming on CPUs. Our analysis shows that the use of GPUs can bring impressive speedups in the presence of complex rules. On the other hand, it shows that multi-core CPUs scale better with the number of rules. Our conclusion is that an advanced CEP engine should leverage a multi-core CPU for processing the simplest rules, using the GPU as a coprocessor devoted to process the most complex ones.