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机译:基于多核SMT架构的多颗粒Delaunay网格生成方法
Department of Computer and Communications Engineering, University of Thessaly, Volos, Greece;
Lawrence Berkeley National Lab, Berkeley, CA 94720, United States;
Department of Computer Science, The College of William and Mary, Williamsburg, VA 23187, United States;
Department of Computer Science, The College of William and Mary, Williamsburg, VA 23187, United States;
Department of Computer Science. Virginia Tech. Blacksburg, VA 24061, United States;
parallel; mesh generation; delaunay; multigrain; multicore; SMT;
机译:同时多线程架构上Delaunay网格生成的算法,软件和硬件优化
机译:约束质心Voronoi-Delaunay镶嵌生成自适应四面体网格的有限元方法
机译:MRAG-I2D:适用于多核体系结构上的改进涡旋方法的多分辨率自适应网格
机译:基于Delaunay三角剖分的Tetra-Hex混合网格生成方法
机译:用于Delaunay网格生成的可扩展算法。
机译:通过SubOptimal Delaunay三角测量的特征保护表面网格平滑
机译:用于多核smT架构的多粒度Delaunay网格生成方法
机译:Delaunay细化网格生成。